Krishna Kumar P. S. 6/1, 2nd Main, 4th Cross, Dinnur, R.T.Nagar, Bangalore - 560 032, Karnataka, India Phone : 91-80-3335604 E-mail : kkps@ieee.org ------------------------------------------------------------------------------------------------- Objective Become a World Class Professional in the field of Digital Design (Systems / Boards / Chips). ------------------------------------------------------------------------------------------------- Professional experience 1992 Jan - till date Centre for Development Of Telematics, Bangalore, India (The Telecom Technology Centre of the Government of India) Designation: Program Manager ------------------------------------------------------------------------------------------------- Assignments 1. Frame Relay Line Termination Unit (Current project) --------------------------------------------------- The FR-LTU is one of the edge nodes in the C-DOT ATM Switch architecture. It terminates FR subscribers over 2Mbps (G.703) or over the V interfaces, and does segmentation and re-assembly functions towards the ATM core switch side. The system consists of two types of line cards, one controller cum segmentation and re-assembly card and one power supply and clock card. The line cards are PPC403 based and the controller card is PPC603 based. The system uses a 12 layer mother board. Areas of experience ------------------- Project Management, Product design, System design, Hardware design, and FR standards. Team ---- The team consists of 5 Design Engineers, and 1 Project Manager. The team is a part of C-DOT's ATM project. Responsibility -------------- I am the Program Manager for this product. I have handled the following responsibilities: * Generation of product specifications * Design of the product architecture * Co-ordination of the generation of hardware specifications for the cards involved, and review of the same * Review of the Circuit Schematics, CAD Design and CAM Pre-processing of the cards involved * System design including * Design of the mother board connector pin assignments * Design of PCB stack up for the mother board and daughter boards * Design of subscriber cabling * Backplane Signal integrity analysis using CAD tools (Intergraph) * Review of test specifications for the cards involved * Generation of system test plan * Miscellaneous project management activities including * Procurement of components * Procurement of test equipments Tools ----- The High Speed Analyzer Tool from Intergraph for signal integrity analysis. 2. ATM PDH Line Card (APC) (Current project) ----------------------------------------- The APC card is one of the two types of line cards in the C-DOT ATM core switch. It terminates ATM over E3 PDH (G.804 over G.832/G.703). The card extracts the ATM cells from the PDH interface and passes the cells towards the Switch Card over a 50MHz nibble bus. The APC is a 14 layer daughter board that plugs into an 18 layer mother board. The card is PPC403 based. It uses an ATM chipset for the conversion of E3 PDH to the nibble interface, and ALTERA programmable logic for the control logic. Areas of experience ------------------- Hardware design, CAD, CAM pre-processing, Programmable logic design in VHDL and simulation, Tester software, System integration, Testing (using ATM test equipments), and ATM standards. Team ---- The responsibility for the development of a card is of a single person in C-DOT. The different card developments for a project are coordinated by a Program Manager. The various stages in the design of the card are reviewed by the Program Manager and the other design engineers in the team. Responsibility -------------- I was responsible for the design and testing of this card. I have handled the following responsibilities: * Generation of Functional Specifications for the card * Selection of the processor and the ATM chip set to be used in the card * Hardware design, CAD and CAM pre-processing for the card * ALTERA EPLD design (in VHDL) and simulation * Generation of test specifications * Review of tester software * Functionality testing of the card and the tester software * Interface testing using ATM test equipments * Support for system software integration (debugging) * System integration Tools ----- * PCB Engineer (Intergraph) for schematic capture, placement, routing, CAD and CAM pre-processing * ALTERA programmable logic software for VHDL coding and simulation Languages --------- C (tester software), C++ (system software) Testing / Debugging tools ------------------------- Tekelec ATM test equipments, W&G equipment for G.703 analysis, and HP and IBM emulators for PPC403. 3. ATM Cell Switch Element review (Current project) ------------------------------------------------ The ACE is a 64x64 ATM switch fabric being developed in C-DOT for use in future ATM switch designs. Areas of experience ------------------- Architecture of ATM switch fabrics, Hardware design review, and VHDL code review. Team ---- The review team consists of two members. Both the members does the complete review separately and simultaneously. Responsibility -------------- * Review of the architecture of the switch fabric * Review of the VHDL code of the ASIC 4. Value Engineered High Performance Input Output Processor -------------------------------------------------------- The VH-IOP is a computer running UNIX used as the multi user man machine interface to the C-DOT digital switching system. The system is a MC68040 based single card solution for an IOP. Other interfaces supported are: 10 ACIA ports, 7 HDLC ports, 1 X.25 port (all supported using MC68302); an Ethernet port (supported using Intel 82596); a SCSI2 port (supported using NCR 53C710 SCSI controller) for connection to a storage subsystem consisting of a winchester drive, a catridge drive and a floppy drive; and 16MB DRAM. The control logic including the DRAM controller was implemented using ALTERA EPLDs. Areas of experience ------------------- System design, Hardware design, Programmable logic design using ALTERA, CAD design, CAM pre-processing, and ACIA, HDLC, X.25, SCSI and Ethernet standards. Team ---- The team consisted of 2 engineers and a program manager. Responsibility -------------- I was responsible for the hardware design of the single card involved and for the system design (packaging, cabling and cooling). I have handled the following responsibilities: * Generation of functional specifications for the system and the card * Study of the performance requirement of the system * Selections of the devices to be used in the card * Hardware design and theoretical performance analysis * CAD design and CAM pre-processing * EPLD design using ALTERA schematic capture tools * Functional testing and validation * Field support Tools ----- * PCB Engineer (Intergraph) for schematic capture, placement, routing, CAD and CAM pre-processing * ALTERA schematic capture tool for EPLD design Testing / Debugging tools ------------------------- HP emulator for MC68040 5. Tester software for VH-IOP -------------------------- Tester software development is an important step in the product development cycle at C-DOT. Tester software development involves generation of test specifications for a card, designing the tests required to cover the card functionality, and coding. Areas of experience ------------------- Software design, Coding in C. Team ---- The team consisted of two engineers and a program manager. Responsibility -------------- I was responsible for the development of the tester software for the SCSI interface and the Ethernet interface in VH-IOP. Languages --------- C, MC68040 assembly 6. Digital Trunk Interface ASIC ---------------------------- The DTI ASIC was developed in C-DOT envisaging the large scale requirement of the 2Mbps digital trunk interface functionality in the C-DOT switching systems. Areas of experience ------------------- Fault coverage analysis, Hardware design review. Team ---- The team for the DTI ASIC consisted of 2 engineers and a support team. I was a part of the support team. Responsibility -------------- I was responsible for incorporating test vectors for the ASIC so as to improve the fault coverage. The job involved analyzing the circuit schematics of the ASIC, the designer's test vectors and the fault coverage report of the tool and adding new test vectors so as to improve the fault coverage. 7. Remote Switch Unit (RSU) ------------------------ The RSU is the C-DOT implementation of the CCITT idea of a geographically distributed switching system. The C-DOT RSU was implemented using 2Mbps (G.703) digital trunks for remoting the base module in the C-DOT switching system. Areas of experience ------------------- System design, Hardware design, and Programmable logic design using XILINX. Team ---- The team consisted of 3 engineers and a program manager. The job of the team was to develop an architecture for the C-DOT RSU and to design the cards involved. Responsibility -------------- I was responsible for the design of one of the two new cards that were to be developed for the RSU architecture. I was also involved in the architecture design and system design activities for the RSU. I have handled the following responsibilities: * Hardware design of the card involved * Design of the XILINX FPGAs for the control logic * Functionality testing * System integration * Deployment of RSU and Field support * Review of two generation of cards for enhanced RSUs Tools ----- * DAISY tools for schematic entry, placement, routing, and CAM pre-processing * XILINX tools for FPGA design Testing / Debugging tools ------------------------- * Anritsu, GNELMI, Marconi, W&G and HP equipments for G.703 testing * 6805 emulators ------------------------------------------------------------------------------------------------- Skills PCB Design Cycle: Intergraph tools, DAISY tools Programmable logic: ALTERA, XILINX Behavioral languages: VHDL, DABL High speed simulation: Intergraph tools for signal integrity analysis S/W languages: C, C++ ------------------------------------------------------------------------------------------------- Education 1987 - 1991 College of Engineering, Trivandrum B.Tech ( Electronics and Communication Engineering ) Percentage of Marks: 86.2 (Ranked First in the University) ------------------------------------------------------------------------------------------------- Personal Information Date of Birth: 26-03-1970 Sex: Male Permanent Address: T.C. 37 / 763 South Nada Near Vaikundam Kalyana Mandapam Fort P.O. Trivandrum - 695023 Kerala, India ------------------------------------------------------------------------------------------------- Awards received 1. Received the divisional best group award for the development of the ATM core switch 2. Received the divisional award for best performance for the development of the VH-IOP 3. Received the exceptional team award from the CDOT board of directors for the realization of the RSU ------------------------------------------------------------------------------------------------- Certificate Courses Completed continuing education courses conducted by the Indian Institute of Sciences, Bangalore on 1. Object Oriented Programming using C++ 2. Nano Electronic Packaging and Manufacturing Technology -------------------------------------------------------------------------------------------------